The present application relates to integrated circuit fabrication, and more specifically to photolithographic processes used in IC fabrication.
Photolithography is a major element of IC fabrication. Several technologies have been developed to produce resist patterns small enough to meet the size requirements of the industry. Ever decreasing size requirements mean that smaller and smaller resist patterns must be placed on wafer surfaces to etch the necessary features. Alignment of wafers has therefore become an important part of IC fabrication, since misalignments that once were within pattern tolerance are no longer acceptable.
Alignment of wafers is accomplished in a variety of ways. Typically, marks are placed on wafer surfaces that indicate the correct placement of the wafer within the exposure system, so that when the wafer is exposed, the exposure pattern will correctly lie with respect to previous underlying patterns already present on a wafer. In some applications, where gates and other features require extremely precise pattern alignment, errors on the order of tens of nanometers must be corrected. This requires an alignment procedure capable of consistently placing patterns to within such a tolerance.
High resolution lithographic tools, such as steppers and step-and-scan tools, are used to print multiple patterns, or shots, on a substrate. Though methods vary, generally a stepper samples several shots, or single exposures of a pattern on the wafer surface, to check the wafer alignment. According to the overall map for the chip pattern, several shots are sampled, each containing alignment information in the form of one or more alignment marks. Steppers use software xe2x80x9crecipes,xe2x80x9d where a separate family of recipes exists for each device being fabricated, and where each recipe samples certain shots to optimize alignment for that particular device.
Alignment marks determine the offset needed to properly align the wafer, typically in cartesian coordinates. There will often be separate marks for x-direction and y-direction orientation, though combinational marks also exist that align the wafer in both directions with a single mark structure. The information gathered from the alignment marks can be in many forms, such as a digital image of the mark or an interference pattern corresponding to the mark""s orientation and location. The exact method depends on many factors, such as the material used, planarization, etc. Different device fabrication procedures and different exposure systems therefore use different sampling modes to gather information from the alignment marks.
Alignment systems in general are designed for a given device fabrication using a given pattern exposure system. Though the optics used in IC fabrication exposure are among the best in the world, distortion still exists, and as device sizes decrease even the best optics available produce distortion that can cause pattern alignment failure.
During printing of a device, a given level is printed and alignment marks are made for orienting and aligning the wafer when a later level of the device is exposed. Each subsequent pattern is aligned to marks on the wafer which were printed at one of the previous pattern steps. However, during printing, the patterns may be minutely displaced in the x- and y-direction, depending on their positions in the imaging field and on the lens distortion associated with that position. This displacement is controlled as much as possible, but remains significant compared to the alignment tolerance. Alignment marks themselves also experience this displacement, depending on which area of the lens is used to print each mark on a given device. This arises from the fact that different sections of the lens produce different distortion in an image.
One solution to this problem has been to compile databases of information on every device type (numbering in the hundreds) and every exposure system (often fifteen or more) to create custom offsets that predict and compensate for the distortions of a given device layer. These databases quickly grow to immense size, and often are useless when changes are made to device processes or new devices are introduced.
In recent alignment systems, several alignment marks are sampled from each of several shots, and then averaged to produce a total alignment for the wafer. Though this method minimizes the need for custom offset databases, it is time consuming. A wafer spends a certain amount of time on the tool for preparation (including alignment of the wafer), printing, and overhead tasks. As an example, alignment for only one x and y alignment mark per shot on 8 shots per wafer may take 20 seconds out of a total 90 seconds on the wafer in a typical system. If eight marks are used for averaging, the alignment time increases to 160 seconds, adding 140 seconds to the entire process and reducing throughput to 40%.
The IC fabrication art would therefore benefit from a process which obtained the advantages of multi-sample averaging without the drastic reduction in throughput.
Shot Averaging for Fine Pattern Alignment with Minimal Through-Put Loss
The present application discloses a method of shot averaging that uses information gathered from the first wafer of a batch to derive alignment mark relationships on later wafers. This innovative process alleviates the need to measure the locations of all alignment marks on succeeding wafers of a batch.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following:
fewer measurements taken of alignment marks;
increase in throughput without loss of alignment accuracy;
the advantages of alignment mark averaging across a shot is obtained.